Research: FPGA-based Architecture For Efficient And High-performance Detector - Dr. Ahmed Ammari

In this research project, we are working on an efficient image features extraction descriptor using hardware implementation on field programmable gate array (FPGA) to accelerators the process.

This image-based detection system is aimed to work in real-time and to be area-efficient with high detection accuracy. The hardware implementation on an FPGA is dedicated to accelerators the covariance matrix feature descriptor. Due to the performance of the covariance descriptor is found to be superior to other methods, as rotation and illumination changes are absorbed by the covariance matrix.